Silent Access

When enabled (CTRLA.SILACC = 1), the silent access feature allows to store data and their 1's complement in the TRAM thus reducing the overall data reading noise, as always the same number of '0' and '1' will be read for each read access.
Note: Silent access bit must be configured before CTRLA.ENABLE is set. This setting cannot be changed while the module is enabled.

When silent access is enabled , the logical size of the TRAM is divided by two to store each byte of data and its 1’s complement (CompData) in the whole physical TRAM size .

The differential write and silent read processes are transparent and managed by the TRAM controller , The TRAM executes the following process on data access :

• When the CPU writes to the TRAM, the data and its bit-wise invert are stored into the RAM.

• When the CPU reads from the TRAM, both the data and its bit-wise invert are retrieved from the RAM. If the TRAM cannot verify that both values complement each other, a bus error is returned.

When silent access is enabled , the data stored in the TRAM must be accessed using the logical mapping shown in TRAM logical mapping table:

Table 1. TRAM logical mapping (CTRLA.SILACC=1)
Byte 3 Byte 2 Byte 1 Byte 0 TRAM Register
Data Data Data Data RAM0
... ... ... ... ...
Data Data Data Data RAM[63]
Reserved Reserved Reserved Reserved RAM[64]
... ... ... ... ...
Reserved Reserved Reserved Reserved RAM[127]

Only 8-bit (byte) access and 16-bit (half-word) access are supported in this mode. 32-bit (word) write accesses are ignored and 32-bit (word) read accesses return 0.

All accesses to the reserved area of the TRAM are discarded and generate a bus error.

The physical mapping of the TRAM when silent access is enabled, is represented in TRAM physical mapping table:

Table 2. TRAM physical mapping (CTRLA.SILACC=1)
Byte 3 Byte 2 Byte 1 Byte 0 TRAM Register
CompData Data CompData Data RAM0
CompData Data CompData Data RAM1
CompData Data CompData Data RAM2
... ... ... ... ...
CompData Data CompData Data RAM[127]

When used in addition of data scrambling , the TRAM controller automatically manage both scrambling and differential data storage operation on specific data access.