INTENSET

Interrupt Enable Set

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
  0x05 8 PAC Write-Protection 0x00  
Parent topic: Register Description

Interrupt Enable Set

Bit  7 6 5 4 3 2 1 0  
              EMPTY UNDERRUN  
Access              R/W R/W  
Reset              0 0  

Bit 1 – EMPTY: Data Buffer Empty Interrupt Enable

Data Buffer Empty Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Data Buffer Empty Interrupt Enable bit, which enables the Data Buffer Empty interrupt.

ValueDescription
0 The Data Buffer Empty interrupt is disabled.
1 The Data Buffer Empty interrupt is enabled.

Bit 0 – UNDERRUN: Underrun Interrupt Enable

Underrun Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Data Buffer Underrun Interrupt Enable bit, which enables the Data Buffer Underrun interrupt.

ValueDescription
0 The Data Buffer Underrun interrupt is disabled.
1 The Data Buffer Underrun interrupt is enabled.