DPLLPRESC

DPLL Prescaler

  0x38 8 PAC Write-Protection, Write-Synchronized 0x00  
Parent topic: Register Description

DPLL Prescaler

Bit  7 6 5 4 3 2 1 0  
              PRESC[1:0]  
Access              R/W R/W  
Reset              0 0  

Bits 1:0 – PRESC[1:0]: Output Clock Prescaler

Output Clock Prescaler

These bits define the output clock prescaler setting.

ValueNameDescription
0x0 DIV1 DPLL output is divided by 1
0x1 DIV2 DPLL output is divided by 2
0x2 DIV4 DPLL output is divided by 4
0x3 Reserved