Due to asynchronicity between the main clock
domain and the peripheral clock domains, some registers need to be synchronized when
written or read.
The following bits are synchronized when written:
- Software Reset bit in Control A
register, CTRLA.SWRST
- Enable bit in Control A register,
CTRLA.ENABLE
- Count Read Synchronization bit in Control A
register (CTRLA.COUNTSYNC)
- Clock Read Synchronization bit in Control A
register (CTRLA.COUNTSYNC)
The following registers are
synchronized when written:
- Counter Value register, COUNT
- Clock Value register, CLOCK
- Counter Period register, PER
- Compare n Value registers, COMPn
- Alarm n Value registers, ALARMn
- Frequency Correction register,
FREQCORR
- Alarm n Mask register, MASKn
- The General Purpose n registers (GPn)
The following registers are
synchronized when read:
- The Counter Value register, COUNT, if
the Counter Read Sync Enable bit in CTRLA (CTRLA.COUNTSYNC) is '1'
- The Clock Value register, CLOCK, if
the Clock Read Sync Enable bit in CTRLA (CTRLA.CLOCKSYNC) is '1'
- The Timestamp Value register
(TIMESTAMP)
Required write-synchronization
is denoted by the "Write-Synchronized" property in the register description.
Required
read-synchronization is denoted by the "Read-Synchronized" property in the register
description.