Due to asynchronicity between the main clock
domain and the peripheral clock domains, some registers need to be synchronized when
written or read.
The following bits are synchronized when written:
- Software Reset bit in Control A register (CTRLA.SWRST)
- Enable bit in Control A register (CTRLA.ENABLE)
The following registers are
synchronized when written:
- Input Control register (INPUTCTRL)
- Control C register (CTRLC)
- Average control register (AVGCTRL)
- Sampling time control register
(SAMPCTRL)
- Window Monitor Lower Threshold register
(WINLT)
- Window Monitor Upper Threshold register
(WINUT)
- Gain correction register (GAINCORR)
- Offset Correction register
(OFFSETCORR)
- Software Trigger register (SWTRIG)
Required write-synchronization
is denoted by the "Write-Synchronized" property in the register description.