CHINTENCLR

Channel Interrupt Enable Clear

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Channel Interrupt Enable Set (CHINTENSET) register.

This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).

  0x4C 8 PAC Write-Protection 0x00  
Parent topic: Register Description

Channel Interrupt Enable Clear

Bit  7 6 5 4 3 2 1 0  
            SUSP TCMPL TERR  
Access            R/W R/W R/W  
Reset            0 0 0  

Bit 2 – SUSP: Channel Suspend Interrupt Enable

Channel Suspend Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Channel Suspend Interrupt Enable bit, which disables the Channel Suspend interrupt.

ValueDescription
0 The Channel Suspend interrupt is disabled.
1 The Channel Suspend interrupt is enabled.

Bit 1 – TCMPL: Channel Transfer Complete Interrupt Enable

Channel Transfer Complete Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Channel Transfer Complete Interrupt Enable bit, which disables the Channel Transfer Complete interrupt.

ValueDescription
0 The Channel Transfer Complete interrupt is disabled. When block action is set to none, the TCMPL flag will not be set when a block transfer is completed.
1 The Channel Transfer Complete interrupt is enabled.

Bit 0 – TERR: Channel Transfer Error Interrupt Enable

Channel Transfer Error Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Channel Transfer Error Interrupt Enable bit, which disables the Channel Transfer Error interrupt.

ValueDescription
0 The Channel Transfer Error interrupt is disabled.
1 The Channel Transfer Error interrupt is enabled.