DFLLULP Dither Control
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PER[2:0] | STEP[2:0] | ||||||||
| Access | R | R/W | R/W | R/W | R | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Dither Period
These bits define the number of reference clock periods over which dithering is applied.
| Value | Name | Description |
|---|---|---|
| 0x0 | PER1 | Dither over 1 reference clock period |
| 0x1 | PER2 | Dither over 2 reference clock periods |
| 0x2 | PER4 | Dither over 4 reference clock periods |
| 0x3 | PER8 | Dither over 8 reference clock periods |
| 0x4 | PER16 | Dither over 16 reference clock periods |
| 0x5 | PER32 | Dither over 32 reference clock periods |
| 0x6 - 0x7 | - | Reserved |
Dither Step
This field defines the dithering step size.
| Value | Name | Description |
|---|---|---|
| 0x0 | STEP1 | Dither step = 1 |
| 0x1 | STEP2 | Dither step = 2 |
| 0x2 | STEP4 | Dither step = 4 |
| 0x3 | STEP8 | Dither step = 8 |
| 0x4 - 0x7 | - | Reserved |