TAMPCTRL

Tamper Control

  0x60 32 PAC Write-Protection, Enable-Protected 0x00000000    
Parent topic: Register Description - Mode 0 - 32-Bit Counter

Tamper Control

Bit  31 30 29 28 27 26 25 24  
          DEBNC3 DEBNC2 DEBNC1 DEBNC0  
Access                   
Reset          0 0 0 0  
Bit  23 22 21 20 19 18 17 16  
          TAMLVL3 TAMLVL2 TAMLVL1 TAMLVL0  
Access                   
Reset          0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
  IN3ACT[1:0] IN2ACT[1:0] IN1ACT[1:0] IN0ACT[1:0]  
Access                   
Reset  0 0 0 0 0 0 0 0  

Bits 24, 25, 26, 27 – DEBNCn: Debounce Enable of Tamper Input INn [n=0..3]

Debounce Enable of Tamper Input INn [n=0..3]

Note: Debounce feature does not apply to the Active Layer Protection mode (TAMPCTRL.INACT = ACTL).
ValueDescription
0 Debouncing is disabled for Tamper input INn
1 Debouncing is enabled for Tamper input INn

Bits 16, 17, 18, 19 – TAMLVLn: Tamper Level Select of Tamper Input INn [n=0..3]

Tamper Level Select of Tamper Input INn [n=0..3]

Note: Tamper Level feature does not apply to the Active Layer Protection mode (TAMPCTRL.INACT = ACTL).
ValueDescription
0 A falling edge condition will be detected on Tamper input INn.
1 A rising edge condition will be detected on Tamper input INn.

Bits 0:1, 2:3, 4:5, 6:7 – INnACT[1:0]: Tamper Channel n Action [n=0..3]

Tamper Channel n Action [n=0..3]

These bits determine the action taken by Tamper Channel n.
ValueNameDescription
0x0 OFF Off (Disabled)
0x1 WAKE Wake and set Tamper flag
0x2 CAPTURE Capture timestamp and set Tamper flag
0x3 ACTL Compare RTC signal routed between INn and OUT pins . When a mismatch occurs, capture timestamp and set Tamper flag