INTENSET

Interrupt Enable Set

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
  0x05 8 PAC Write-Protection 0x00  
Parent topic: Register Description

Interrupt Enable Set

Bit  7 6 5 4 3 2 1 0  
                EW  
Access                R/W  
Reset                0  

Bit 0 – EW: Early Warning Interrupt Enable

Early Warning Interrupt Enable

Writing a '0' to this bit has no effect.


Writing a '1' to this bit sets the Early Warning Interrupt Enable bit, which enables the Early Warning interrupt.

ValueDescription
0 The Early Warning interrupt is disabled.
1 The Early Warning interrupt is enabled.