INTENSET

Interrupt Enable Set

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
  0x04 32 PAC Write-Protection 0x00000000  
Parent topic: Register Description

Interrupt Enable Set

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
          ULPVREFRDY VCORERDY   VREGRDY  
Access          R/W R/W   R/W  
Reset          0 0   0  
Bit  7 6 5 4 3 2 1 0  
            B33SRDY BOD33DET BOD33RDY  
Access            R/W R/W R/W  
Reset            0 0 0  

Bit 11 – ULPVREFRDY: Low Power Voltage Reference Ready Interrupt Enable

Low Power Voltage Reference Ready Interrupt Enable

Writing a '0' to this bit has no effect.

The ULPVREFRDY bit is set on a zero-to-one transition of the Low Power Voltage Reference Ready bit in the Status register (STATUS.ULPVREFRDY).

ValueDescription
0 The Low Power Ready interrupt is disabled.
1 The Low Power Ready interrupt is enabled and an interrupt request will be generated when the ULPVREFRDY Interrupt Flag is set.

Bit 10 – VCORERDY: VDDCORE Voltage Ready Interrupt Enable

VDDCORE Voltage Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the VDDCORE Ready Interrupt Enable bit, which enables the VDDCORE Ready interrupt.

ValueDescription
0 The VDDCORE Ready interrupt is disabled.
1 The VDDCORE Ready interrupt is enabled and an interrupt request will be generated when the VCORERDY Interrupt Flag is set.

Bit 8 – VREGRDY: Voltage Regulator Ready Interrupt Enable

Voltage Regulator Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Voltage Regulator Ready Interrupt Enable bit, which enables the Voltage Regulator Ready interrupt.

ValueDescription
0 The Voltage Regulator Ready interrupt is disabled.
1 The Voltage Regulator Ready interrupt is enabled and an interrupt request will be generated when the Voltage Regulator Ready Interrupt Flag is set.

Bit 2 – B33SRDY: BOD33 Synchronization Ready Interrupt Enable

BOD33 Synchronization Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the BOD33 Synchronization Ready Interrupt Enable bit, which enables the BOD33 Synchronization Ready interrupt.

ValueDescription
0 The BOD33 Synchronization Ready interrupt is disabled.
1 The BOD33 Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the BOD33 Synchronization Ready Interrupt flag is set.

Bit 1 – BOD33DET: BOD33 Detection Interrupt Enable

BOD33 Detection Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the BOD33 Detection Interrupt Enable bit, which enables the BOD33 Detection interrupt.

ValueDescription
0 The BOD33 Detection interrupt is disabled.
1 The BOD33 Detection interrupt is enabled, and an interrupt request will be generated when the BOD33 Detection Interrupt flag is set.

Bit 0 – BOD33RDY: BOD33 Ready Interrupt Enable

BOD33 Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the BOD33 Ready Interrupt Enable bit, which enables the BOD33 Ready interrupt.

ValueDescription
0 The BOD33 Ready interrupt is disabled.
1 The BOD33 Ready interrupt is enabled, and an interrupt request will be generated when the BOD33 Ready Interrupt flag is set.