By default, in Standby Sleep mode, the RAMs, NVM, and
regulators are automatically set in Low-Power mode to reduce power consumption:
- The RAM is in Low-Power mode if its power domain is
in retention or off state.
- Non-Volatile Memory - the NVM is located in the power domain
PDSW. By default, the NVM is
automatically set in low power mode in these conditions:
- When the power domain
PDSW is in retention or off
state.
- When the device is in Standby
Sleep mode and the NVM is not accessed. This behavior can be changed by
software by configuring the SLEEPPRM bit group of the CTRLB register in the
NVMCTRL peripheral.
- When the device is in Idle
Sleep mode and the NVM is not accessed. This behavior can be changed by
software by configuring the SLEEPPRM bit group of the CTRLB register in the
NVMCTRL peripheral.
- Regulators: by default, in Standby
Sleep mode, the PM analyzes the device activity to use either the main or the
low-power voltage regulator to supply the VDDCORE.
GCLK clocks, regulators and RAM are not affected in Idle Sleep mode and will
operate as normal.
Table 1. Regulators,
RAMs, and NVM state in Sleep Mode| Sleep Mode |
PDSW |
SRAM Mode(1) |
NVM |
Regulators |
|---|
| |
|
VDDCORE |
|---|
| |
|
main |
ULP |
|---|
| Active |
active |
normal |
normal |
on |
on |
| Idle |
active |
auto(2) |
on |
on |
on |
| Standby - PDSW in
Active mode |
active |
normal(6) |
auto(2) |
auto(3) |
on(5) |
| Standby - PDSW in
Retention mode |
retention |
low power(6) |
low power |
auto(4) |
on(5) |
| OFF |
off |
off |
off |
off |
off |
Notes:
- 1.RAMs mode by default: STDBYCFG.BBIAS
bits are set to their default value.
- 2.auto: by default, NVM is in low-power
mode if not accessed.
- 3.auto: by default, the main voltage
regulator is on if GCLK, APBx, or AHBx clock is running during SleepWalking.
- 4.auto: by default ULP regulator is selected in retention, but main regulator will be
selected if VREG RUNSTDBY register bit in Supply Controller is set to 1.
- 5.on:
low power voltage reference must be ready, and this is confirmed if STATUS.ULPVREFRDY
register bit in SUPC equals to 1
- 6.SRAM can be partially retained in STANDBY using SRAM Power Switch