The following table gives the configuration for the ARM Cortex-M23 processor.
Features | Cortex-M23 Configurable Options | SAM L10 Implementation | SAM L11 Implementation |
---|---|---|---|
Memory Protection Unit (MPU) | Not present, 4, 8, 12, or 16 regions | One MPU with 4 regions | Two MPUs with 4 regions each (one Secure / one Non-Secure) |
Security Attribute Unit (SAU) | Absent, 4-region, or 8-region | Absent | Absent |
Implementation Defined Attribution Unit (IDAU) | Present or Absent | Absent | Present |
SysTick timer(s) | Absent, 1 timer or 2 timers (one Secure and one Non-Secure) | One SysTick timer | Two timers (One Secure / One Non-Secure) |
Vector Table Offset Register | Present or absent | Present (one Vector table) | Present (two Vector tables) |
Reset all registers | Present or absent | Absent | Absent |
Multiplier | Fast (one cycle) or slow (32 cycles) | Fast (one cycle) | Fast (one cycle) |
Divider | Fast (17 cycles) or slow (34 cycles) | Fast (17 cycles) | Fast (17 cycles) |
Interrupts | External interrupts 0-240 | 45(1) | 45(1) |
Instruction fetch width | 16-bit only or 32-bit | 32-bit | 32-bit |
Single-cycle I/O port | Present or absent | Present | Present |
Architectural clock gating present | Present or absent | Present | Present |
Data endianness | Little-endian or big-endian | Little-endian | Little-endian |
Halting debug support | Present or absent | Present | Present |
Wake-up interrupt controller (WIC) | Present or absent | Absent | Absent |
Number of breakpoint comparators | 0, 1, 2, 3, 4 | 4 | 4 |
Number of watchpoint comparators | 0, 1, 2, 3, 4 | 2 | 2 |
Cross Trigger Interface (CTI) | Present or absent | Absent | Absent |
Micro Trace Buffer (MTB) | Present or absent | Absent | Absent |
Embedded Trace Macrocell (ETM) | Present or absent | Absent | Absent |
JTAGnSW debug protocol | Selects between JTAG or Serial-Wire interfaces for the DAP | Serial-Wire | Serial-Wire |
Multi-drop for Serial Wire | Present or absent | Absent | Absent |
For more details, refer to the ARM Cortex-M23 Processor Technical Reference Manual (www.arm.com).