FIN |
Input Clock Frequency |
|
32 |
- |
2000 |
kHz |
FOUT |
Output Clock Frequency |
PL2 |
32 |
- |
96 |
MHz |
PL0 |
32 |
- |
48 |
MHz |
Jp |
Period jitter |
PL0, Fin = 32 kHz, Fout = 32 MHz |
- |
3 |
6 |
% |
PL2, = 32 kHz, Fout = 32 MHz |
- |
2 |
6 |
PL0, Fin = 32 kHz, Fout = 48 MHz |
- |
3 |
4 |
PL2, Fin = 32 kHz, Fout = 48 MHz |
- |
2 |
6 |
PL2, Fin = 32 kHz, Fout = 96 MHz |
- |
3 |
4 |
PL0, Fin = 32 kHz, Fout = 32 MHz |
- |
3 |
5 |
PL2, Fin = 32 kHz, Fout = 32 MHz |
- |
3 |
6 |
PL0, Fin = 2 MHz, Fout = 48 MHz |
- |
5 |
7 |
PL2, Fin = 2 MHz, Fout = 48 MHz |
- |
3 |
6 |
PL2, Fin= 2 MHz, Fout= 96 MHz |
- |
4 |
10 |
tLOCK |
Lock Time |
After startup, time to get lock signal Fin = 32 kHz,
Fout = 96 MHz |
- |
1.1 |
1.5 |
ms |
After startup, time to get lock signal Fin = 2 MHz, Fout
= 96 MHz |
- |
24 |
35 |
µs |
Duty |
Duty cycle (1) |
|
40 |
50 |
60 |
% |