INTENSET

Interrupt Enable Set

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
  0x09 8 PAC Write-Protection 0x00  

Interrupt Enable Set

Bit  7 6 5 4 3 2 1 0  
      MC1 MC0     ERR OVF  
Access      R/W R/W     R/W R/W  
Reset      0 0     0 0  

Bits 4, 5 – MCx: Match or Capture Channel x Interrupt Enable

Match or Capture Channel x Interrupt Enable

Writing a '0' to these bits has no effect.

Writing a '1' to MCx will clear the corresponding Match or Capture Channel x Interrupt Enable bit, which disables the Match or Capture Channel x interrupt.

ValueDescription
0 The Match or Capture Channel x interrupt is disabled.
1 The Match or Capture Channel x interrupt is enabled.

Bit 1 – ERR: Error Interrupt Enable

Error Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.

ValueDescription
0 The Error interrupt is disabled.
1 The Error interrupt is enabled.

Bit 0 – OVF: Overflow Interrupt Enable

Overflow Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt request.

ValueDescription
0 The Overflow interrupt is disabled.
1 The Overflow interrupt is enabled.