Interrupt Enable Clear

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
  0x08 8 PAC Write-Protection 0x00  

Interrupt Enable Clear

Bit  7 6 5 4 3 2 1 0  
Access                R/W  
Reset                0  

Bit 0 – DATARDY: Data Ready Interrupt Enable

Data Ready Interrupt Enable

Writing a '1' to this bit will clear the Data Ready Interrupt Enable bit, which disables the corresponding interrupt request.

0 The DATARDY interrupt is disabled.
1 The DATARDY interrupt is enabled.