Control A

  0x00 8 PAC Write-Protection 0x00  

Control A

Bit  7 6 5 4 3 2 1 0  
  LPMUX           ENABLE SWRST  
Access  R/W           R/W R/W  
Reset  0           0 0  

Bit 7 – LPMUX: Low-Power Mux

Low-Power Mux

0 The analog input muxes have low resistance, but consume more power at lower voltages (e.g., are driven by the voltage doubler).
1 The analog input muxes have high resistance, but consume less power at lower voltages (e.g., the voltage doubler is disabled).

Bit 1 – ENABLE: Enable


0 The peripheral is disabled.
1 The peripheral is enabled. Each OPAMP must also be enabled individually by the Enable bit in the corresponding OPAMP Control register (OPAMPCTRLx.ENABLE).

Bit 0 – SWRST: Software Reset

Software Reset

Writing a '0' to this bit has no effect.

Writing a '1' to this bit resets all registers in the MODULE to their initial state, and the OPAMP will be disabled.

Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded.

0 There is no reset operation ongoing.
1 The reset operation is ongoing.