BTCNT

Block Transfer Count

The BTCNT register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
  0x02 16 -    

Block Transfer Count

Bit  15 14 13 12 11 10 9 8  
  BTCNT[15:8]  
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
  BTCNT[7:0]  
Access                   
Reset                   

Bits 15:0 – BTCNT[15:0]: Block Transfer Count

Block Transfer Count

This bit group holds the 16-bit block transfer count.

During a transfer, the internal counter value is decremented by one after each beat transfer. The internal counter is written to the corresponding write-back memory section for the DMA channel when the DMA channel loses priority, is suspended or gets disabled. The DMA channel can be disabled by a complete transfer, a transfer error or by software.