Standby Configuration
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BBIASTR | BBIASHS | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| VREGSMOD[1:0] | DPGPDSW | PDCFG | |||||||
| Access | R | R | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Back Bias for TrustRAM
Refer to RAM Automatic Low Power Mode for details.
| Value | Description |
|---|---|
| 0 | Retention Back Biasing mode |
| 1 | Standby Back Biasing mode |
Back Bias for HMCRAMCHS
Refer to RAM Automatic Low Power Mode for details.
| Value | Description |
|---|---|
| 0 | Retention Back Biasing mode |
| 1 | Standby Back Biasing mode |
VREG Switching Mode
Refer to Regulator Automatic Low-Power Mode for details.
| Value | Name | Description |
|---|---|---|
| 0x0 | AUTO | Automatic Mode |
| 0x1 | PERFORMANCE | Performance oriented |
| 0x2 | LP | Low Power consumption oriented |
Dynamic Power Gating for Switchable Power Domain
| Value | Description |
|---|---|
| 0 | Dynamic SleepWalking for switchable power domain is disabled |
| 1 | Dynamic SleepWalking for switchable power domain PDSW is enabled |
Power Domain Configuration
| Value | Name | Description |
|---|---|---|
| 0x0 | DEFAULT | In standby mode, all power domain switching are handled by hardware. |
| 0x1 | PDSW | In standby mode, PDSW is forced ACTIVE. |