Maximum Clock Frequencies

Table 1. Maximum GCLK Generator Output Frequencies(1)
Symbol Description Conditions Fmax Units
PL0 PL2
Fgclkgen[0:2] GCLK Generator output Frequency - 24 96 MHz
Fgclkgen[3:4] - 12 48 MHz
Note:
  1. 1.These values are based on simulation. They are not covered by production test limits or characterization.
Table 2. Maximum Peripheral Clock Frequencies(1)
Symbol Description Conditions Fmax. Units
PL0 PL2
fCPU CPU clock frequency - 8 32 MHz
fAHB AHB clock frequency - 8 32 MHz
fAPBA APBA clock frequency - 8 32 MHz
fAPBB APBB clock frequency -
fAPBC APBC clock frequency -
fGCLK_DFLLULP DFLLULP Reference clock frequency - 33 33 kHz
fGCLK_DPLL FDPLL96M Reference clock frequency - 2 2 MHz
fGCLK_DPLL_32K FDPLL96M 32K clock frequency - 32.768 32.768 kHz
fGCLK_EIC EIC input clock frequency - 12 48 MHz
fGCLK_EVSYS_CHANNEL_0 EVSYS channel 0 input clock frequency - 12 48 MHz
fGCLK_EVSYS_CHANNEL_1 EVSYS channel 1 input clock frequency -
fGCLK_EVSYS_CHANNEL_2 EVSYS channel 2 input clock frequency -
fGCLK_EVSYS_CHANNEL_3 EVSYS channel 3 input clock frequency -
fGCLK_SERCOM0_SLOW Common SERCOM0 slow input clock frequency - 1 5 MHz
fGCLK_SERCOM1_SLOW Common SERCOM1 slow input clock frequency -
fGCLK_SERCOM2_SLOW Common SERCOM2 slow input clock frequency -
fGCLK_SERCOM0_CORE SERCOM0 input clock frequency - 12 48 MHz
fGCLK_SERCOM1_CORE SERCOM1 input clock frequency -
fGCLK_SERCOM2_CORE SERCOM2 input clock frequency -
fGCLK_TC0 TC0 input clock frequency - 12 48 MHz
fGCLK_TC1 TC1 input clock frequency -
f GCLK_TC2 TC2 input clock frequency -
fGCLK_ADC ADC input clock frequency - 12 48 MHz
fGCLK_AC AC digital input clock frequency -
fGCLK_DAC DAC input clock frequency -
fGCLK_FREQM_MSR FREQM measured clock frequency -
fGCLK_FREQM_REF FREQM reference clock frequency -
fGCLK_PTC PTC input clock frequency -
fGCLK_CCL CCL input clock frequency -
fGCLKin External GCLK input clock frequency -
Note:
  1. 1.These values are based on simulation. They are not covered by production test limits or characterization.