INTENSET

Interrupt Enable Set

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
  0x05 8 PAC Write-Protection 0x00  
Parent topic: Register Description

Interrupt Enable Set

Bit  7 6 5 4 3 2 1 0  
                PLRDY  
Access                R/W  
Reset                0  

Bit 0 – PLRDY: Performance Level Ready Interrupt Enable

Performance Level Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Performance Ready Interrupt Enable bit and enable the Performance Ready interrupt.

ValueDescription
0 The Performance Ready interrupt is disabled.
1 The Performance Ready interrupt is enabled.