BOD33

3.3V Brown-Out Detector (BOD33) Control

  0x10 32 Write-Synchronized, Enable-Protected, PAC Write-Protection x initially determined from NVM User Row after reset  
Parent topic: Register Description

3.3V Brown-Out Detector (BOD33) Control

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
      LEVEL[5:0]  
Access      R/W R/W R/W R/W R/W R/W  
Reset      x x x x x x  
Bit  15 14 13 12 11 10 9 8  
  PSEL[3:0] VREFSEL     ACTCFG  
Access  R/W R/W R/W R/W R/W     R/W  
Reset  0 0 0 0 0     0  
Bit  7 6 5 4 3 2 1 0  
    RUNSTDBY STDBYCFG ACTION[1:0] HYST ENABLE    
Access    R/W R/W R/W R/W R/W R/W    
Reset    0 0 x x x x    

Bits 21:16 – LEVEL[5:0]: BOD33 Threshold Level on VDD

BOD33 Threshold Level on VDD

These bits set the triggering voltage threshold for the BOD33 when the BOD33 monitors the VDD.

These bits are loaded from NVM User Row at start-up.

This bit field is not synchronized.

Bits 15:12 – PSEL[3:0]: Prescaler Select

Prescaler Select

Selects the prescaler divide-by output for the BOD33 sampling mode. The input clock comes from the OSCULP32K 1 KHz output.

This bit field is not synchronized.

ValueNameDescription
0x0 DIV2 Divide clock by 2
0x1 DIV4 Divide clock by 4
0x2 DIV8 Divide clock by 8
0x3 DIV16 Divide clock by 16
0x4 DIV32 Divide clock by 32
0x5 DIV64 Divide clock by 64
0x6 DIV128 Divide clock by 128
0x7 DIV256 Divide clock by 256
0x8 DIV512 Divide clock by 512
0x9 DIV1024 Divide clock by 1024
0xA DIV2048 Divide clock by 2048
0xB DIV4096 Divide clock by 4096
0xC DIV8192 Divide clock by 8192
0xD DIV16384 Divide clock by 16384
0xE DIV32768 Divide clock by 32768
0xF DIV65536 Divide clock by 65536

Bit 11 – VREFSEL: BOD33 Voltage Reference Selection

BOD33 Voltage Reference Selection

This bit is not synchronized.

ValueDescription
0 Selects VREF for the BOD33.
1 Selects ULPVREF for the BOD33.

Bit 8 – ACTCFG: BOD33 Configuration in Active Sleep Mode

BOD33 Configuration in Active Sleep Mode

This bit is not synchronized.

ValueDescription
0 In active mode, the BOD33 operates in continuous mode.
1 In active mode, the BOD33 operates in sampling mode.

Bit 6 – RUNSTDBY: Run in Standby

Run in Standby

This bit is not synchronized.

ValueDescription
0 In standby sleep mode, the BOD33 is disabled.
1 In standby sleep mode, the BOD33 is enabled.

Bit 5 – STDBYCFG: BOD33 Configuration in Standby Sleep Mode

BOD33 Configuration in Standby Sleep Mode

If the RUNSTDBY bit is set to '1', the STDBYCFG bit sets the BOD33 configuration in standby sleep mode.

This bit is not synchronized.

ValueDescription
0 In standby sleep mode, the BOD33 is enabled and configured in continuous mode.
1 In standby sleep mode, the BOD33 is enabled and configured in sampling mode.

Bits 4:3 – ACTION[1:0]: BOD33 Action

BOD33 Action

These bits are used to select the BOD33 action when the supply voltage crosses below the BOD33 threshold.

These bits are loaded from NVM User Row at start-up.

This bit field is not synchronized.

Value Name Description
0x0 NONE No action
0x1 RESET The BOD33 generates a reset
0x2 INT The BOD33 generates an interrupt
0x3 -

Reserved

Bit 2 – HYST: Hysteresis

Hysteresis

This bit indicates whether hysteresis is enabled for the BOD33 threshold voltage.

This bit is loaded from NVM User Row at start-up.

This bit is not synchronized.

ValueDescription
0 No hysteresis.
1 Hysteresis enabled.

Bit 1 – ENABLE: Enable

Enable

This bit is loaded from NVM User Row at start-up.

This bit is not enable-protected.

ValueDescription
0 BOD33 is disabled.
1 BOD33 is enabled.