Control A
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CMDEX[7:0] | |||||||||
| Access | W/W*/W | W/W*/W | W/W*/W | W/W*/W | W/W*/W | W/W*/W | W/W*/W | W/W*/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CMD[6:0] | |||||||||
| Access | W/W/W | W/W/W | W/W/W | W/W/W | W/W/W | W/W/W | W/W/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Command Execution
When this bit group is written to the key value 0xA5, the command written to CMD will be executed. If a value different from the key value is tried, the write will not be performed and the key error interrupt (INTFLAG.KEYE) will be set. PROGE is set if a previously written command is not completed yet or in case of bad conditions.
The key value must be written at the same time as CMD. If a command is issued through the APB bus on the same cycle as an AHB bus access, the AHB bus access will be given priority. The command will then be executed when the NVM block and the AHB bus are idle.
STATUS.READY must be '1' when the command has issued.
Command
These bits define the command to be executed when the CMDEX key is written.
| CMD[6:0] | Group Configuration | Description |
|---|---|---|
| 0x00-0x01 | - | Reserved |
| 0x02 | ER | Erase Row - Erases the row addressed by the ADDR register in the Flash, Data Flash or NVM Rows. |
| 0x03 | - | Reserved |
| 0x04 | WP | Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. |
| 0x05-0x41 | - | Reserved |
| 0x42 | SPRM | Sets the Power Reduction Mode. |
| 0x43 | CPRM | Clears the Power Reduction Mode. |
| 0x44 | PBC | Page Buffer Clear - Clears the page buffer. |
| 0x45 | - | Reserved |
| 0x46 | INVALL | Invalidates all cache lines. |
| 0x47-0x4A | - | Reserved |
| 0x4B | SDAL0 | Set DAL=0 |
| 0x4C (SAM L10 ) | Reserved | Reserved |
| 0x4C (SAM L11 ) | SDAL1 | Set DAL=1 |
| 0x4D-0x7F | - | Reserved |