Due to asynchronicity between the main clock
domain and the peripheral clock domains, some registers need to be synchronized when
written or read.
The following bits are synchronized when written:
- Software Reset bit in the CTRLA register (CTRLA.SWRST)
- Enable bit in the CTRLA register (CTRLA.ENABLE)
- Receiver Enable bit in the CTRLB register (CTRLB.RXEN)
- Transmitter Enable bit in the Control B register (CTRLB.TXEN)
Note: CTRLB.RXEN is write-synchronized somewhat
differently. See also
CTRLB for details.
Required write-synchronization
is denoted by the "Write-Synchronized" property in the register description.