DFLLULP Synchronization Busy
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DELAY | ENABLE | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
Delay Register Synchronization Busy
This bit is cleared when the synchronization of DFLLULPDLY is complete.
This bit is set when the synchronization of DFLLULPDLY is started.
Writing this bit has no effect.
Enable Bit Synchronization Busy
This bit is cleared when the synchronization of DFLLULPCTRL.ENABLE is complete.
This bit is set when the synchronization of DFLLULPCTRL.ENABLE is started.
Writing this bit has no effect.