INTENCLR

Interrupt Enable Clear

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
  0x04 8 PAC Write-Protection 0x00  
Parent topic: Register Description

Interrupt Enable Clear

Bit  7 6 5 4 3 2 1 0  
            WINMON OVERRUN RESRDY  
Access            R/W R/W R/W  
Reset            0 0 0  

Bit 2 – WINMON: Window Monitor Interrupt Enable

Window Monitor Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Window Monitor Interrupt Enable bit, which disables the corresponding interrupt request.

ValueDescription
0 The window monitor interrupt is disabled.
1 The window monitor interrupt is enabled, and an interrupt request will be generated when the Window Monitor interrupt flag is set.

Bit 1 – OVERRUN: Overrun Interrupt Enable

Overrun Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Overrun Interrupt Enable bit, which disables the corresponding interrupt request.

ValueDescription
0 The Overrun interrupt is disabled.
1 The Overrun interrupt is enabled, and an interrupt request will be generated when the Overrun interrupt flag is set.

Bit 0 – RESRDY: Result Ready Interrupt Enable

Result Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Result Ready Interrupt Enable bit, which disables the corresponding interrupt request.

ValueDescription
0 The Result Ready interrupt is disabled.
1 The Result Ready interrupt is enabled, and an interrupt request will be generated when the Result Ready interrupt flag is set.