“CPU reset extension” refers to the extension of the reset phase
of the CPU core after the external reset is released. This ensures that the CPU is not
executing code at startup while a debugger connects to the system. It is detected on a
RESET release event when SWCLK is low. At startup, SWCLK is
internally pulled up to avoid false detection of a debugger if SWCLK is left
unconnected. When the CPU is held in the reset extension phase, the CPU Reset Extension
bit of the Status A register (STATUSA.CRSTEXT) is set. To release the CPU, write a '1'
to STATUSA.CRSTEXT. STATUSA.CRSTEXT will then be set to zero. Writing a '0' to
STATUSA.CRSTEXT has no effect. Releasing the "CPU reset extension" is possible for all
DAL levels. The CPU then executes the Boot ROM that offers basic failure analysis
services and security checks. It is not possible to access the bus system until the Boot
ROM has performed these security checks.
Note: Refer to Boot ROM for more information.
Figure 1. Typical CPU Reset Extension Set and Clear Timing Diagram
