INTENCLR

Interrupt Enable Clear in Clock/Calendar mode (CTRLA.MODE=2)

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
  0x08 16 PAC Write-Protection 0x0000    
Parent topic: Register Description - Mode 2 - Clock/Calendar

Interrupt Enable Clear in Clock/Calendar mode (CTRLA.MODE=2)

Bit  15 14 13 12 11 10 9 8  
  OVF TAMPER           ALARM0  
Access  R/W R/W           R/W  
Reset  0 0           0  
Bit  7 6 5 4 3 2 1 0  
  PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bit 15 – OVF: Overflow Interrupt Enable

Overflow Interrupt Enable

Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt.
ValueDescription
0 The Overflow interrupt is disabled.
1 The Overflow interrupt is enabled.

Bit 14 – TAMPER: Tamper Interrupt Enable

Tamper Interrupt Enable

Bit 8 – ALARM0: Alarm 0 Interrupt Enable

Alarm 0 Interrupt Enable

Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Alarm 0 Interrupt Enable bit, which disables the Alarm interrupt.
ValueDescription
0 The Alarm 0 interrupt is disabled.
1 The Alarm 0 interrupt is enabled.

Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn: Periodic Interval n Interrupt Enable [n = 7..0]

Periodic Interval n Interrupt Enable [n = 7..0]

Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Periodic Interval n Interrupt Enable bit, which disables the Periodic Interval n interrupt.
ValueDescription
0 Periodic Interval n interrupt is disabled.
1 Periodic Interval n interrupt is enabled.