ASYNCH

External Interrupt Asynchronous Mode

Important: For SAM L11 Non-Secure accesses, read and write accesses (RW*) are allowed only if the external interrupt x (EXTINTx) is set as Non-Secure in the NONSEC register (NONSEC.EXTINTx bit). Some restrictions apply for the Non-Secure accesses to an Enable-Protected register as it will not be possible for the Non-Secure to configure it once this register is enabled by the Secure application. This will require some veneers to be implemented on Secure side.
  0x18 32 PAC Write-Protection, Enable-Protected, Mix-Secure 0x00000000  
Parent topic: Register Description

External Interrupt Asynchronous Mode

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
  ASYNCH[7:0]  
Access  RW/RW*/RW RW/RW*/RW RW/RW*/RW RW/RW*/RW RW/RW*/RW RW/RW*/RW RW/RW*/RW RW/RW*/RW  
Reset  0 0 0 0 0 0 0 0  

Bits 7:0 – ASYNCH[7:0]: Asynchronous Edge Detection Mode

Asynchronous Edge Detection Mode

The bit x of ASYNCH set the Asynchronous Edge Detection Mode for the interrupt associated with the EXTINTx pin.

ValueDescription
0 The EXTINT x edge detection is synchronously operated.
1 The EXTINT x edge detection is asynchronously operated.