External Interrupt Sense Configuration
Important: For SAM
L11 Non-Secure
accesses, read and write accesses (RW*) are allowed only if the external interrupt x
(EXTINTx) is set as Non-Secure in the NONSEC register (NONSEC.EXTINTx bit). Some
restrictions apply for the Non-Secure accesses to an Enable-Protected register as it
will not be possible for the Non-Secure to configure it once this register is enabled by
the Secure application. This will require some veneers to be implemented on the Secure
side.
0x1C |
32 |
PAC Write-Protection, Enable-Protected, Mix-Secure |
0x00000000 |
|
Input Sense
Configuration x [x=7..0]
These bits define on
which edge or level the interrupt or event for EXTINT[x] will be
generated.
Value | Name | Description |
---|
0x0 |
NONE |
No
detection |
0x1 |
RISE |
Rising-edge
detection |
0x2 |
FALL |
Falling-edge
detection |
0x3 |
BOTH |
Both-edge
detection |
0x4 |
HIGH |
High-level
detection |
0x5 |
LOW |
Low-level
detection |
0x6 -
0x7 |
- |
Reserved |