If a bus error is received from an AHB client during a DMA data transfer, the corresponding active channel is disabled and the corresponding Channel Transfer Error Interrupt flag in the Channel Interrupt Status and Clear register (CHINTFLAG.TERR) is set. If enabled, the optional transfer error interrupt is generated. The transfer counter will not be decremented and its current value is written-back in the write-back memory section before the channel is disabled.
When the DMAC fetches an invalid descriptor
(BTCTRL.VALID=0
) or when the channel is resumed and the DMA fetches the
next descriptor with null address (DESCADDR=0x00000000), the corresponding channel
operation is suspended, the Channel Suspend Interrupt Flag in the Channel Interrupt Flag
Status and Clear register (CHINTFLAG.SUSP) is set, and the Channel Fetch Error bit in the
Channel Status register (CHSTATUS.FERR) is set. If enabled, the optional suspend interrupt
is generated.