Interrupt Enable Clear
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
ERROR | DRDY | AMATCH | PREC | ||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Error Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.
Value | Description |
---|---|
0 | Error interrupt is disabled. |
1 | Error interrupt is enabled. |
Data Ready Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Data Ready bit, which disables the Data Ready interrupt.
Value | Description |
---|---|
0 | The Data Ready interrupt is disabled. |
1 | The Data Ready interrupt is enabled. |
Address Match Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Address Match Interrupt Enable bit, which disables the Address Match interrupt.
Value | Description |
---|---|
0 | The Address Match interrupt is disabled. |
1 | The Address Match interrupt is enabled. |
Stop Received Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Stop Received Interrupt Enable bit, which disables the Stop Received interrupt.
Value | Description |
---|---|
0 | The Stop Received interrupt is disabled. |
1 | The Stop Received interrupt is enabled. |