INTENCLR

Interrupt Enable Clear

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
  0x14 8 PAC Write-Protection 0x00  
Parent topic: Register Description

Interrupt Enable Clear

Bit  7 6 5 4 3 2 1 0  
  ERROR         DRDY AMATCH PREC  
Access  R/W         R/W R/W R/W  
Reset  0         0 0 0  

Bit 7 – ERROR: Error Interrupt Enable

Error Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will clear the Error Interrupt Enable bit, which disables the Error interrupt.

ValueDescription
0 Error interrupt is disabled.
1 Error interrupt is enabled.

Bit 2 – DRDY: Data Ready Interrupt Enable

Data Ready Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will clear the Data Ready bit, which disables the Data Ready interrupt.

ValueDescription
0 The Data Ready interrupt is disabled.
1 The Data Ready interrupt is enabled.

Bit 1 – AMATCH: Address Match Interrupt Enable

Address Match Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will clear the Address Match Interrupt Enable bit, which disables the Address Match interrupt.

ValueDescription
0 The Address Match interrupt is disabled.
1 The Address Match interrupt is enabled.

Bit 0 – PREC: Stop Received Interrupt Enable

Stop Received Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will clear the Stop Received Interrupt Enable bit, which disables the Stop Received interrupt.

ValueDescription
0 The Stop Received interrupt is disabled.
1 The Stop Received interrupt is enabled.