Block Transfer Control
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
STEPSIZE[2:0] | STEPSEL | DSTINC | SRCINC | BEATSIZE[1:0] | |||||
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
BLOCKACT[1:0] | EVOSEL[1:0] | VALID | |||||||
Access | |||||||||
Reset |
Address Increment Step Size
These bits select the address increment step size. The setting apply to source or destination address, depending on STEPSEL setting.
Value | Name | Description |
---|---|---|
0x0 | X1 | Next ADDR = ADDR + (Beat size in byte) * 1 |
0x1 | X2 | Next ADDR = ADDR + (Beat size in byte) * 2 |
0x2 | X4 | Next ADDR = ADDR + (Beat size in byte) * 4 |
0x3 | X8 | Next ADDR = ADDR + (Beat size in byte) * 8 |
0x4 | X16 | Next ADDR = ADDR + (Beat size in byte) * 16 |
0x5 | X32 | Next ADDR = ADDR + (Beat size in byte) * 32 |
0x6 | X64 | Next ADDR = ADDR + (Beat size in byte) * 64 |
0x7 | X128 | Next ADDR = ADDR + (Beat size in byte) * 128 |
Step Selection
This bit selects if source or destination addresses are using the step size settings.
Value | Name | Description |
---|---|---|
0x0 | DST | Step size settings apply to the destination address |
0x1 | SRC | Step size settings apply to the source address |
Destination Address Increment Enable
Writing a '0' to this bit will disable the destination address incrementation. The address will be kept fixed during the data transfer.
Writing a '1' to this bit will enable the destination address incrementation. By default, the destination address is incremented by 1. If the STEPSEL bit is cleared, flexible step-size settings are available in the STEPSIZE register.
Value | Description |
---|---|
0 | The Destination Address Increment is disabled. |
1 | The Destination Address Increment is enabled. |
Source Address Increment Enable
Writing a '0' to this bit will disable the source address incrementation. The address will be kept fixed during the data transfer.
Writing a '1' to this bit will enable the source address incrementation. By default, the source address is incremented by 1. If the STEPSEL bit is set, flexible step-size settings are available in the STEPSIZE register.
Value | Description |
---|---|
0 | The Source Address Increment is disabled. |
1 | The Source Address Increment is enabled. |
Beat Size
These bits define the size of one beat. A beat is the size of one data transfer bus access, and the setting apply to both read and write accesses.
Value | Name | Description |
---|---|---|
0x0 | BYTE | 8-bit bus transfer |
0x1 | HWORD | 16-bit bus transfer |
0x2 | WORD | 32-bit bus transfer |
other | Reserved |
Block Action
These bits define what actions the DMAC should take after a block transfer has completed.
BLOCKACT[1:0] | Name | Description |
---|---|---|
0x0 | NOACT | Channel will be disabled if it is the last block transfer in the transaction |
0x1 | INT | Channel will be disabled if it is the last block transfer in the transaction and block interrupt |
0x2 | SUSPEND | Channel suspend operation is completed |
0x3 | BOTH | Both channel suspend operation and block interrupt |
Event Output Selection
These bits define the event output selection.
EVOSEL[1:0] | Name | Description |
---|---|---|
0x0 | DISABLE | Event generation disabled |
0x1 | BLOCK | Event strobe when block transfer complete |
0x2 | Reserved | |
0x3 | BEAT | Event strobe when beat transfer complete |
Descriptor Valid
Writing a '0' to this bit in the Descriptor or Write-Back memory will suspend the DMA channel operation when fetching the corresponding descriptor.
The bit is automatically cleared in the Write-Back memory section when channel is aborted, when an error is detected during the block transfer, or when the block transfer is completed.
Value | Description |
---|---|
0 | The descriptor is not valid. |
1 | The descriptor is valid. |