In this step, the functionality of the HDL is verified after Synthesis using a testbench. In
libero.tcl
, use the following command to run post-synthesis
simulation.
run_tool -name {SIM_POSTSYNTH}
Use this command with the catch
statement as shown in the following
snippet.
if {[catch {run_tool -name {SYNTHESIZE} }] } {
puts "SIM_POSTSYNTH FAILED \n"
} else {
puts "SIM_POSTSYNTH PASSED \n"
}
For more information about adding Synthesis parameters, see Tcl Commands Reference Guide for Libero SoC Design Suite.