Pre-Synthesis Simulation

In this step, the functionality of the HDL is verified before Synthesis using a testbench. In libero.tcl, use the following command to run pre-synthesis simulation.

Copyrun_tool -name {SIM_PRESYNTH}

As a best practice, use this command with the catch statement as shown in the following snippet.

Copyif {[catch {run_tool -name {SIM_PRESYNTH}  }] } {
	  puts "SIM_PRESYNTH FAILED \n"
   } else {
	  puts "SIM_PRESYNTH PASSED \n"
   }  

For more information about adding pre-synthesis simulation parameters, see Tcl Commands Reference Guide for Libero SoC Design Suite.