HDL Files

In this step, the following tasks are executed:
  1. 1.Creating a Libero SoC project.
  2. 2.Importing all the HDL, constraints, and stimulus source files that are required for the project.
  3. 3.Building the design hierarchy by defining the top module.

In libero.tcl, use the following commands to execute these tasks.

source ./parameters.tcl;

set libero_cmd "new_project \
                -location {./exprj} -name {exprj} \
                -family {$prj_family} -die {$prj_die} -package {$prj_package} \
                -speed {$prj_speed} \
                -hdl {VERILOG}";

eval file delete -force ./exprj;

eval $libero_cmd;

source ./design.tcl;

build_design_hierarchy;

set_root $prj_root;

For more information about HDL commands, see Tcl Commands Reference Guide for Libero SoC Design Suite.