Natural Order (Hardware) Priority

When vectored interrupts are enabled and more than one interrupt with the same user specified priority level is requested, the priority conflict is resolved by using a method called “Natural Order Priority”. Natural order priority is a fixed priority scheme that is based on the IVT.

Table 1. Interrupt Vector Priority Table
Vector

Number

Interrupt

source

Vector

Number

(cont.)

Interrupt

source

(cont.)

0x0 Software Interrupt 0x27 PWM1GINT
0x1 INT0 0x28 PWM2RINT
0x2 INT1 0x29 PWM2GINT
0x3 INT2 0x2A CWG1 (Complementary Waveform Generator)
0x4 DMA1SCNT (Direct Memory Access) 0x2B CLC1 (Configurable Logic Cell)
0x5 DMA1DCNT 0x2C CLC2
0x6 DMA1OR 0x2D CLC3
0x7 DMA1A 0x2E CLC4
0x8 DMA2SCNT (Direct Memory Access) 0x2F IOCV (Interrupt-On-Change Virtual Ports)
0x9 DMA2DCNT 0x30 U1RX
0xA DMA2OR 0x31 U1TX
0xB DMA2A 0x32 U1
0xC DMA3SCNT 0x33 U1E
0xD DMA3DCNT 0x34 U2RX
0xE DMA3OR 0x35 U2TX
0xF DMA3A 0x36 U2
0x10 DMA4SCNT 0x37 U2E
0x11 DMA4DCNT 0x38 SPI1RX (Serial Peripheral Interface)
0x12 DMA4OR 0x39 SPI1TX
0x13 DMA4A 0x3A SPI1
0x14 NVM 0x3B I2C1RX
0x15 CRC (Cyclic Redundancy Check) 0x3C I2C1TX
0x16 SCAN 0x3D I2C1
0x17 ACT (Active Clock Tuning) 0x3E I2C1E
0x18 CSW (Clock Switching) 0x3F -
0x19 OSF (Oscillator Fail) 0x40 I3C1RX
0x1A VDDIO2 0x41 I3C1TX
0x1B VDDIO3 0x42 I3C1
0x1C IOC (Interrupt-On-Change) 0x43 I3C1E
0x1D TMR0 0x44 I3C1R
0x1E TMR1 0x45 I3C2RX
0x1F TMR1G 0x46 I3C2TX
0x20 TMR2 0x47 I3C2
0x21 TMR4 0x48 - 0x4B I3C2E
0x22 TU16A (Universal Timer 16A) 0x4C I3C2R
0x23 TU16B (Universal Timer 16B) 0x4D HLVD (High/Low-Voltage Detect)
0x24 CCP1 (Capture/Compare/PWM) 0x4E AD (ADC Conversion Complete)
0x25 CCP2 (Capture/Compare/PWM) 0x4F ADT (ADC Threshold)
0x26 PWM1RINT 0x50 -

The natural order priority scheme goes from high-to-low with increasing vector numbers, with 0 being the highest priority and decreasing from there.

For example, when two concurrently occurring interrupt sources that are both designated high priority, using the IPRx register will be resolved using the natural order priority (i.e., the interrupt with a lower corresponding vector number will preempt the interrupt with the higher vector number).

The ability for the user to assign every interrupt source to high- or low-priority levels means that the user program can give an interrupt with a low natural priority, a higher overall priority level.