I3C Pad Compatibility with I2C/SMBus Levels

The I3C Target module can be used in I2C mode (OPMD = 0b00) until it is assigned a Dynamic Address. However, the module’s operating mode does not switch the SDA/SCL pads to become I2C/SMBus compatible.
Outside of enabling the I3C module (EN = 1), for the I3C SDA and SCL pads to become compliant with I2C/SMBus voltage levels, the Threshold TH bits in the corresponding RxyI2C register must select the appropriate I2C/SMBus Buffer. This selection disables the Standard GPIO and the I3C Low-Voltage Buffers. The desired slew rate and pull-ups can also be selected using the SLEW and PU bits in the RxyI2C register. Refer to the “I2C Pad Control” section in the “I/O Ports” chapter.
In addition to buffer selection in the pads, the I3CxI2CCON register provides additional settings for I2C/SMBus compatibility of the I3C module. The 50 ns Spike Filters can be enabled on the SDA/SCL lines by setting the FLTEN bit. This selection allows the module to ignore bus traffic at higher I3C speeds. An appropriate SDA Hold Time can also be selected using the SDAHT bits to ensure valid data transfers at various bus speeds and capacitance loads.