Pin Allocation Tables

Table 1. 14-Pin Allocation Table
I/O 14-Pin SOIC/TSSOP A/D Reference Timers 16-Bit PWM/CCP CWG CLC SPI I2C

I3C®

UART IOC Interrupts Basic
RA0 13 ANA0 IOCA0

ICDDAT
ICSPDAT

RA1 12 ANA1

VREF+ (ADC)

TUIN0(1) IOCA1

ICDCLK
ICSPCLK

RA2 11 ANA2

VREF- (ADC)

T0CKI(1) CWG1IN(1) IOCA2 INT0(1)
RA3 4 IOCA3

MCLR
VPP

RA4 3 ANA4

T1G(1)

IOCA4 INT1(1)

CLKOUT
SOSCO
OSC2

RA5 2 ANA5

T1CKI(1)
T2IN(1)

PWM1ERS(1) CLCIN3(1) IOCA5 INT2(1)

CLKIN
SOSCI
OSC1

RC0(7) 10 TUIN1(1) SCK1(1) SCL1(3,4) I3C1_SCL(5) CTS2(1) IOCC0
RC1(7) 9 T4IN(1)

PWM2ERS(1)

CLCIN2(1) SDI1(1) SDA1(3,4) I3C1_SDA(5) RX2(1) IOCC1
RC3 7

ANC3
ADACT(1)

CCP2IN(1)
PWMIN1(1)

CLCIN0(1) SS1(1) (3,4) IOCC3
RC4 6 ANC4 CLCIN1(1)   (3,4) CTS1(1) IOCC4
RC5 5 ANC5

CCP1IN(1) PWMIN0(1)

RX1(1) IOCC5
VDD 1 VDD
VDDIO2 8 VDDIO2
VSS 14 VSS
OUT(2)

ADCGRDA
ADCGRDB

TMR0
TU16A
TU16B

PWM11
PWM12
PWM21
PWM22
CCP1
CCP2

CWG1A
CWG1B
CWG1C
CWG1D

CLC1OUT
CLC2OUT
CLC3OUT
CLC4OUT

SS1
SCK1
SDO1

SDA1
SCL1

DTR1
RTS1
TX1
DTR2
RTS2
TX2

Notes:
  1. 1.This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
  2. 2.All digital output signals shown in these rows are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options.
  3. 3.This is a bidirectional signal. For normal module operation, the firmware will map this signal to the same pin in both the PPS input and PPS output registers.
  4. 4. These pins are configured for I2C logic levels; the SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
  5. 5.These pins are configured for I3C® logic levels and are not PPS remappable. MVIO must be enabled on these pins to be compliant with the I3C bus standards.
  6. 6. A 0.1 uF bypass capacitor to VSS is required on the VDD pin.
  7. 7.MVIO pins, powered by VDDIO2.
Table 2. 20-Pin Allocation Table
I/O 20-Pin

PDIP/
SOIC/
SSOP

20-Pin VQFN A/D Reference Timers 16-Bit PWM/CCP CWG CLC SPI I2C

I3C®

UART IOC Interrupts Basic
RA0 19 16 ANA0   IOCA0

ICDDAT
ICSPDAT

RA1 18 15 ANA1

VREF+ (ADC)

TUIN0(1) IOCA1

ICDCLK
ICSPCLK

RA2 17 14 ANA2

VREF- (ADC)

T0CKI(1) CWG1IN(1) CLCIN0(1) IOCA2 INT0(1)
RA3 4 1 IOCA3

MCLR
VPP

RA4 3 20 ANA4

T1G(1)

IOCA4 INT1(1)

CLKOUT
SOSCO
OSC2

RA5 2 19 ANA5


T2IN(1)
T1CKI(1)

PWM1ERS

(1)

IOCA5 INT2(1)

CLKIN
SOSCI
OSC1

RB5(8) 12 9 CLCIN3(1) SDI1(1) SDA1(3,4) I3C2_SDA(5) RX1(1) IOCB5
RB6(8) 11 8 CLCIN2(1) SCK1(1) SCL1(3,4) I3C2_SCL(5) IOCB6
RB7 10 7 ANB7 CTS1(1) IOCB7
RC0(7) 16 13 TUIN1(1) (3,4) I3C1_SCL(5) CTS2(1) IOCC0
RC1(7) 15 12 T4IN(1) PWM2ERS

(1)

(3,4) I3C1_SDA(5) RX2(1) IOCC1
RC3 7 4

ANC3
ADACT(1)


CCP2IN(1)
PWMIN1(1)

CLCIN1(1) IOCC3
RC4 6 3 ANC4 T3G(1) (3,4) IOCC4
RC5 5 2 ANC5

T3CKI(1)

CCP1IN(1)
PWMIN0(1)

(3,4) IOCC5
RC6 8 5 ANC6 SS1(1) IOCC6
RC7 9 6 ANC7 IOCC7
VDD 1 18 VDD
VDDIO2 14 11 VDDIO2
VDDIO3 13 10 VDDIO3
VSS 20 17 VSS
OUT(2)

ADCGRDA
ADCGRDB

TMR0
TU16A
TU16B

PWM11
PWM12
PWM21
PWM22
CCP1
CCP2

CWG1A
CWG1B
CWG1C
CWG1D

CLC1OUT
CLC2OUT
CLC3OUT
CLC4OUT

SS1
SCK1
SDO1

SDA1
SCL1

DTR1
RTS1
TX1
DTR2
RTS2
TX2

Notes:
  1. 1.This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
  2. 2.All digital output signals shown in these rows are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options.
  3. 3.This is a bidirectional signal. For normal module operation, the firmware will map this signal to the same pin in both the PPS input and PPS output registers.
  4. 4. These pins are configured for I2C logic levels; the SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
  5. 5.These pins are configured for I3C® logic levels and are not PPS remappable. MVIO must be enabled on these pins to be compliant with the I3C bus standards.
  6. 6.A 0.1 uF bypass capacitor to VSS is required on the VDD pin.
  7. 7.MVIO pins, powered by VDDIO2.
  8. 8.MVIO pins, powered by VDDIO3.