Error Type TE2 occurs when the Target receives an invalid write data. The Target detects
this error by performing a parity check on the T-Bit following the write data byte that
is received from the Controller. This error can be detected either during CCC transfer
or Private transfer. The
TE2ERR bit and the
BUSEIF Bus Error Interrupt Flag are set upon successful detection of TE2
type error. Once set, the TE2ERR and BUSEIF bits will not self-clear. The user must
clear them in software to re-arm the functionality of each bit individually.
The Target recovers from this error by ignoring any following patterns on the bus and
then waits for the next Stop or Restart condition. If the error is detected after
receiving a CCC, the Target retains the CCC state until the end of the CCC command.