PIR8

PIR8

Peripheral Interrupt Request Register 8
Notes:
  1. 1. Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
  2. 2.I3C1RIF is a read-only bit.
  3. 3.I3C1EIF is a read-only bit. To clear the interrupt condition, all bits in the I3C1ERRIRx registers must be cleared.
  4. 4.I3C1IF is a read-only bit. To clear the interrupt condition, all bits in the I3C1PIRx registers must be cleared.
  5. 5.I3C1TXIF is a read-only bit. The interrupt flag is cleared when I3CxTXB Transmit Buffer becomes full.
  6. 6. I3C1RXIF is a read-only bit. The interrupt flag is cleared when I3CxRXB Receive Buffer becomes empty.
0x471 8  

PIR8

Bit  7 6 5 4 3 2 1 0  
        I3C1RIF I3C1EIF I3C1IF I3C1TXIF I3C1RXIF  
Access        R R R R R  
Reset        0 0 0 0 0  

Bit 4 – I3C1RIF: I3C1 Reset Interrupt Flag(2)

I3C1 Reset Interrupt Flag

(2)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 3 – I3C1EIF: I3C1 Error Interrupt Flag(3)

I3C1 Error Interrupt Flag

(3)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 2 – I3C1IF: I3C1 General Interrupt Flag(4)

I3C1 General Interrupt Flag

(4)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 1 – I3C1TXIF: I3C1 Transmit Interrupt Flag(5)

I3C1 Transmit Interrupt Flag

(5)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 0 – I3C1RXIF: I3C1 Receive Interrupt Flag(6)

I3C1 Receive Interrupt Flag

(6)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred