ADCON3

ADCON3

ADC Control Register 3
  0x232 8  

ADCON3

Bit  7 6 5 4 3 2 1 0  
    CALC[2:0] SOI TMD[2:0]  
Access    R/W R/W R/W R/W/HC R/W R/W R/W  
Reset    0 0 0 0 0 0 0  

Bits 6:4 – CALC[2:0]: ADC Error Calculation Mode Select

ADC Error Calculation Mode Select

Table 1. ADC Error Calculation Mode
CALC ADERR Application
DSEN = 0 Single-Sample Mode DSEN = 1 CVD Double-Sample Mode(1)
111 Reserved Reserved Reserved
110 Reserved Reserved Reserved
101 ADFLTR-ADSTPT ADFLTR-ADSTPT Average/filtered value vs. setpoint
100 ADPREV-ADFLTR ADPREV-ADFLTR First derivative of filtered value(3) (negative)
011 Reserved Reserved Reserved
010 ADRES-ADFLTR (ADRES-ADPREV)-ADFLTR Actual result vs. averaged/filtered value
001 ADRES-ADSTPT (ADRES-ADPREV)-ADSTPT Actual result vs. setpoint
000 ADRES-ADPREV ADRES-ADPREV First derivative of single measurement(2)
Actual CVD result(2)
Notes:
  1. 1.When DSEN = 1 and PSIS = 0, ADERR is computed only after every second sample.
  2. 2.When PSIS = 0.
  3. 3.When PSIS = 1.

Bit 3 – SOI: ADC Stop-on-Interrupt

ADC Stop-on-Interrupt

ValueNameDescription
x CONT = 0 This bit is not used
1 CONT = 1 GO is cleared when the Threshold conditions are met, otherwise the conversion is retriggered
0 CONT = 1 GO is not cleared by hardware, must be cleared by software to stop retriggers

Bits 2:0 – TMD[2:0]: Threshold Interrupt Mode Select

Threshold Interrupt Mode Select

ValueDescription
111 Interrupt regardless of threshold test results
110 Interrupt if ADERR > ADUTH
101 Interrupt if ADERR ≤ ADUTH
100 Interrupt if ADERR < ADLTH or ADERR > ADUTH
011 Interrupt if ADERR > ADLTH and ADERR < ADUTH
010 Interrupt if ADERR ≥ ADLTH
001 Interrupt if ADERR < ADLTH
000 Never interrupt