Host Clock Timing

The Serial Clock (SCL) signal is generated by module hardware via the I2C Clock Selection (I2CxCLK) register, the I2C Baud Rate Prescaler (I2CxBAUD) register, and the Fast Mode Enable (FME) bits.

The figure below illustrates the SCL clock generation.

Figure 1. SCL Clock Generation

I2CxCLK contains several clock source selections. The clock source selections typically include variants of the system clock and timer resources.

Important: When using a timer as the clock source, the timer must also be configured. Additionally, when using the HFINTOSC as a clock source, it is important to understand that the HFINTOSC frequency selected by the OSCFRQ register is used as the clock source. The clock divider selected by the NDIV bits is not used. For example, if OSCFRQ selects 4 MHz as the HFINTOSC clock frequency, and the NDIV bits select a divide by four scaling factor, the I2C Clock Frequency will be 4 MHz and not 1 MHz since the divider is ignored.

I2CxBAUD is used to determine the prescaler (clock divider) for the I2CxCLK source.

The FME bit acts as a secondary divider to the prescaled clock source.

When FME = 0, one SCL period (TSCL) is equal to five clock periods of the prescaled I2CxCLK source. In other words, the prescaled I2CxCLK source is divided by five. For example, if the HFINTOSC (set to 4 MHz) clock source is selected, I2CxBAUD is loaded with a value of ‘7’, and FME = 0, the actual SCL frequency is 100 kHz (see the equation below).

Figure 2. SCL Frequency (FME = 0)
Example:
  • I2CxCLK: HFINTOSC (4 MHz)
  • I2CxBAUD: 7
  • FME: FME = 0
fSCL=fI2CxCLK(BAUD+1)FME=4MHz85=100kHz

When FME = 0, host hardware uses the first prescaled I2CxCLK source period to release SCL, allowing it to float high (see the figure below). Host hardware then uses the second and third periods to sample SCL to verify that SCL is high. If a client is holding SCL low (clock stretch) during the second and/or third period, host hardware samples each successive prescaled I2CxCLK period until a high level is detected on SCL. Once the high level is detected, host hardware samples SCL during the next two I2CxCLK periods to verify that SCL is high. The host hardware then uses the fourth prescaled I2CxCLK source period to drive SCL low. During the fifth period, host hardware verifies that SCL is in fact low.

Figure 3. SCL Timing (FME = 0, up to fSCL = 100 kHz)

When FME = 1, one SCL period (TSCL) is equal to four clock periods of the prescaled I2CxCLK source. In other words, the prescaled I2CxCLK source is divided by four. Using the example from above, if the HFINTOSC (4 MHz) clock source is selected, I2CxBAUD is loaded with a value of ‘7’, and FME = 1, the actual SCL frequency is 125 kHz (see the equation below).

Figure 4. SCL Frequency (FME = 1)
Example:
  • I2CxCLK: HFINTOSC (4 MHz)
  • I2CxBAUD: 7
  • FME: FME = 1
fSCL=fI2CxCLK(BAUD+1)FME=4MHz84=125kHz

When FME = 1, host hardware uses the first prescaled I2CxCLK source period to release SCL, allowing it to float high (see the figure below). Host hardware then uses the second period to sample SCL to verify that SCL is high. If a client is holding SCL low (clock stretch) during the second period, host hardware samples each successive prescaled I2CxCLK period until a high level is detected on SCL. Once the high level is detected, host hardware samples SCL during the next period to verify that SCL is high. The host hardware then uses the third period to drive SCL low. During the fourth prescaled period, host hardware verifies that SCL is in fact low.

Figure 5. SCL Timing (FME = 1, up to fSCL = 400 kHz)

When FME = 2, one SCL period (TSCL) is equal to 16 clock periods of the prescaled I2CxCLK source. In other words, the prescaled I2CxCLK source is divided by 16. Using the example from above, if the HFINTOSC (64 MHz) clock source is selected, I2CxBAUD is loaded with a value of ‘3’, and FME = 2, the actual SCL frequency is 1 MHz (see the equation below).

Figure 6. SCL Frequency (FME = 2, up to fSCL = 1 MHz)
Example:
  • I2CxCLK: HFINTOSC (64 MHz)
  • I2CxBAUD: 3
  • FME: FME = 2
fSCL=fI2CxCLK(BAUD+1)FME=64MHz416=1MHz

When FME = 2, host hardware uses the first prescaled I2CxCLK source period to release SCL, allowing it to float high (see the figure below). Host hardware then uses the sixth period to sample SCL to verify that SCL is high. If a client is holding SCL low (clock stretch) during the sixth period, host hardware samples each successive prescaled I2CxCLK period until a high level is detected on SCL. Once the high level is detected, host hardware samples SCL during the next six I2CxCLK periods to verify that SCL is high. The host hardware then uses the seventh prescaled I2CxCLK source period to drive SCL low. During eighth through sixteenth periods, host hardware verifies that SCL is in fact low.

Figure 7. SCL Timing (FME = 2, up to fSCL = 1 MHz)

The following tables show the different FME Bit Options and Common I2CxBAUD Divider Settings for different modes of I2C operation.

Table 1. Fast Mode Enable (FME) Options
I2C Mode Valid FME Bit Options
Standard mode (Max fSCL = 100 kHz) FME = 0, 1, 2
Fast mode (Max fSCL = 400 kHz) FME = 1, 2
Fast mode+ (Max fSCL = 1 MHz) FME = 2
Table 2. Common I2CxBAUD Divider Settings

I2CxCLK

Osc Freq

fSCL = 1 MHz

FME = 2

fSCL = 400 kHz

FME = 1

fSCL = 100 kHz

FME = 0

fSCL = 10 kHz

FME = 0

I2CxBAUD Values
64 MHz 3 39 159 -
32 MHz 1 19 79 -
16 MHz 0 9 39 -
8 MHz - 4 19 199
4 MHz - - 9 99
2 MHz - - - 49
1 MHz - - - -
500 kHz - - - -