# Acknowledge Sequence Timing

As previously mentioned, the 9th SCL pulse for any transferred address/data byte is reserved for the Acknowledge (ACK) sequence. During an Acknowledge sequence, the transmitting device relinquishes control of the SDA line to the receiving device. At this time, the receiving device must decide whether to pull the SDA line low (ACK) or allow the line to float high (NACK).

An Acknowledge sequence is enabled automatically by module hardware following an address/data byte reception. On the 8th falling edge of SCL, the value of either the ACKDT or ACKCNT bits are copied to the SDA output, depending on the state of I2CxCNT. When I2CxCNT holds a nonzero value (I2CxCNT != 0), the value of ACKDT is copied to SDA (see the figure below). When I2CxCNT reaches a zero count (I2CxCNT = 0), the value of ACKCNT is copied to SDA (see the figure below). In most applications, the value of ACKDT may be zero (ACKDT = 0), which represents an ACK, while the value of ACKCNT may be one (ACKCNT = 1), which represents a NACK.
Figure 1. Acknowledge (ACK) Sequence Timing
Figure 2. Not Acknowledge (NACK) Sequence Timing