DMAnCON1

DMAnCON1

DMA Control Register 1
0x055 8        

DMAnCON1

Bit  7 6 5 4 3 2 1 0  
  DMODE[1:0] DSTP SMR[1:0] SMODE[1:0] SSTP  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 7:6 – DMODE[1:0]: Destination Address Mode Selection

Destination Address Mode Selection

ValueDescription
11 Reserved, do not use
10 Destination Pointer (DMADPTR) is decremented after each transfer
01 Destination Pointer (DMADPTR) is incremented after each transfer
00 Destination Pointer (DMADPTR) remains unchanged after each transfer

Bit 5 – DSTP: Destination Counter Reload Stop

Destination Counter Reload Stop

ValueDescription
1 SIRQEN bit is cleared when destination counter reloads
0 SIRQEN bit is not cleared when destination counter reloads

Bits 4:3 – SMR[1:0]: Source Memory Region Selection

Source Memory Region Selection

ValueDescription
1x Data EEPROM is selected as the DMA source memory
01 Program Flash Memory is selected as the DMA source memory
00 SFR/GPR data space is selected as the DMA source memory

Bits 2:1 – SMODE[1:0]: Source Address Mode Selection

Source Address Mode Selection

ValueDescription
11 Reserved, do not use
10 Source Pointer (DMASPTR) is decremented after each transfer
01 Source Pointer (DMASPTR) is incremented after each transfer
00 Source Pointer (DMASPTR) remains unchanged after each transfer

Bit 0 – SSTP: Source Counter Reload Stop

Source Counter Reload Stop

ValueDescription
1 SIRQEN bit is cleared when source counter reloads
0 SIRQEN bit is not cleared when source counter reloads