UxFIFO

UxFIFO

UART FIFO Status Register
Note:
  1. 1.The BSF instruction will not be used to set RXBE because doing so will clear a byte pending in the transmit shift register when the UxTXB register is empty. Instead, use the MOVWF instruction with a ‘0’ in the TXBE bit location.
  0x1BE,0x1D2 8   1,2 x

UxFIFO

Bit  7 6 5 4 3 2 1 0  
  TXWRE STPMD TXBE TXBF RXIDL XON RXBE RXBF  
Access  R/W/S R/W R/W/S/C R/S/C R/S/C S/C R/W/S/C R/S/C  
Reset  0 0 1 0 1 1 1 0  

Bit 7 – TXWRE: Transmit Write Error Status (must be cleared by software)

Transmit Write Error Status (must be cleared by software)

ValueNameDescription
1 MODE = LIN Host UxP1L was written when a host process was active
1 MODE = LIN Client UxTXB was written when UxP2 = 0 or more than UxP2 bytes have been written to UxTXB since last Break
1 MODE = Address detect UxP1L was written before the previous data in UxP1L was transferred to TX shifter
1 MODE = All A new byte was written to UxTXB when the output FIFO was full
0 MODE = All No error

Bit 6 – STPMD: Stop Bit Detection Mode

Stop Bit Detection Mode

ValueNameDescription
1 STP = 11 Assert UxRXIF at end of first Stop bit
1 STP ≠ 11 Assert UxRXIF at end of last Stop bit
0 STP = xx Assert UxRXIF in middle of first Stop bit

Bit 5 – TXBE: Transmit Buffer Empty Status

Transmit Buffer Empty Status

ValueDescription
1 Transmit buffer is empty. Setting this bit will clear the transmit buffer and output shift register.
0 Transmit buffer is not empty. Software cannot clear this bit.

Bit 4 – TXBF: Transmit Buffer Full Status

Transmit Buffer Full Status

ValueDescription
1 Transmit buffer is full
0 Transmit buffer is not full

Bit 3 – RXIDL: Receive Pin Idle Status

Receive Pin Idle Status

ValueDescription
1 Receive pin is in Idle state
0 UART is receiving Start, Stop, Data, Auto-baud, or Break

Bit 2 – XON: Software Flow Control Transmit Enable Status

Software Flow Control Transmit Enable Status

ValueDescription
1 Transmitter is enabled
0 Transmitter is disabled

Bit 1 – RXBE: Receive Buffer Empty Status

Receive Buffer Empty Status

ValueDescription
1 Receive buffer is empty. Setting this bit will clear the RX buffer(1).
0 Receive buffer is not empty. Software cannot clear this bit.

Bit 0 – RXBF: Receive Buffer Full Status

Receive Buffer Full Status

ValueDescription
1 Receive buffer is full
0 Receive buffer is not full