I2CxCON1

I2CxCON1

I2C Control Register 1
Notes:
  1. 1.Software writes to ACKDT must be followed by a minimum SDA setup time before clearing CSTR.
  2. 2.A NACK may still be generated by hardware when bus errors are present as indicated by the I2CxSTAT1 or I2CxERR registers.
  3. 3.This bit can only be set when CSD = 1.
  4. 4.If SCL is high (SCL = 1) when this bit is set, the current clock pulse will complete (SCL = 0) with the proper SCL/SDA timing required for a valid Stop condition; any data in the transmit or receive shift registers will be lost.
0x01E7 8         1 1 x
Parent topic: Register Definitions: I2C Control

I2CxCON1

Bit  7 6 5 4 3 2 1 0  
  ACKCNT ACKDT ACKSTAT ACKT P RXO TXU CSD  
Access  R/W R/W R R R/S/HC R/W/HS R/W/HS R/W  
Reset  0 0 0 0 0 0 0 0  

Bit 7 – ACKCNT: Acknowledge End of Count(2)

Acknowledge End of Count(2)

ValueNameDescription
1 I2CxCNT = 0 Not Acknowledge (NACK) copied to SDA output
0 I2CxCNT = 0 Acknowledge (ACK) copied to SDA output

Bit 6 – ACKDT: Acknowledge Data(1,2)

Acknowledge Data(1,2)

ValueNameDescription
1 Matching received address Not Acknowledge (NACK) copied to SDA output
0 Matching received address Acknowledge (ACK) copied to SDA output
1 I2CxCNT != 0 Not Acknowledge (NACK) copied to SDA output
0 I2CxCNT != 0 Acknowledge (ACK) copied to SDA output

Bit 5 – ACKSTAT: Acknowledge Status (Transmission only)

Acknowledge Status (Transmission only)

ValueDescription
1 Acknowledge was not received for the most recent transaction
0 Acknowledge was received for the most recent transaction

Bit 4 – ACKT: Acknowledge Time Status

Acknowledge Time Status

ValueDescription
1 Indicates that the bus is in an Acknowledge sequence, set on the 8th falling SCL edge
0 Not in an Acknowledge sequence, cleared on the 9th rising SCL edge

Bit 3 – P: Host Stop(4)

Host Stop(4)

ValueNameDescription
1 MMA = 1 Initiate a Stop condition
0 MMA = 1 Cleared by hardware after sending Stop

Bit 2 – RXO: Receive Overflow Status (used only when MODE I2C Mode Select = 0xx or MODE = 11x)(3)

Receive Overflow Status (used only when MODE = 0xx or MODE = 11x)(3)

ValueDescription
1 Set when SMA = 1 and a host receives data when RXBF = 1
0 No client receive Overflow condition

Bit 1 – TXU: Transmit Underflow Status (used only when MODE I2C Mode Select = 0xx or MODE I2C Mode Select = 11x)(3)

Transmit Underflow Status (used only when MODE = 0xx or MODE = 11x)(3)

ValueDescription
1 Set when SMA = 1 and a host transmits data when TXBE = 1
0 No client transmit Underflow condition

Bit 0 – CSD: Clock Stretching Disable (used only when MODE I2C Mode Select = 0xx or MODE I2C Mode Select = 11x)

Clock Stretching Disable (used only when MODE = 0xx or MODE = 11x)

ValueDescription
1 When SMA = 1, the CSTR bit will not be set
0 Client clock stretching proceeds normally