The start event for the counter/timer start is selected using the
START bits in the TUxyHLT register. The available options
include:
- 1.No hardware Start: The counter/timer
starts when the ON bit is set. This is the software-based
start option. Any Stop events are ignored, but will still cause a capture.
- 2.Either edge of the ERS signal
(edge-triggered): The counter/timer starts at the event of either the rising or
falling edge of the ERS signal.
- 3.Rising edge of the ERS signal
(edge-triggered): The counter/timer starts at the event of a rising edge of the ERS
signal. When the EPOL bit is set, the polarity is inverted and
the counter/timer starts at the event of a falling edge of ERS signal. See Figure 3 for an example of rising ERS edge Start and either ERS edge Stop
condition.
- 4.ERS =
1 (level-triggered): The counter/timer
starts at the presence of a logic one of the ERS signal. When the EPOL bit is set,
the polarity is inverted and the counter/timer starts at the presence of a logic
zero of the ERS signal. Any Stop events that occur when ERS = 1 (or
0, based on EPOL) are ignored, but will still cause a capture.
See Figure 4 for an example of level-triggered Start.
Important:
- 1. In the event of a
level-triggered Start/Reset, the active level must be asserted for at least
one timer clock period to ensure proper sampling. If the duration of the
asserted level is less than one timer clock, there is a possibility of the
level trigger being missed and not sampled by the timer module.