ADC Control Register 2
  1. 1.To correctly calculate an average, the number of samples (set in ADRPT) must be 2CRS.
  2. 2.CRS = ‘b111 and ‘b000 are reserved.
  3. 3.This bit is cleared by hardware when the accumulator operation is complete; depending on oscillator selections, the delay may be many instructions.
  4. 4.See the “Computation Operation” section for full mode descriptions.
  0x231 8  


Bit  7 6 5 4 3 2 1 0  
  PSIS CRS[2:0] ACLR MD[2:0]  
Access  R/W R/W R/W R/W R/W/HC R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bit 7 – PSIS: ADC Previous Sample Input Select

ADC Previous Sample Input Select

1 ADFLTR is transferred to ADPREV at the start of conversion
0 ADRES is transferred to ADPREV at the start of conversion

Bits 6:4 – CRS[2:0]: ADC Accumulated Calculation Right Shift Select

ADC Accumulated Calculation Right Shift Select

1 to 6 MD = ‘b100 Low-pass filter time constant is 2CRS, filter gain is 1:1(2)
1 to 6 MD = ‘b011 to ‘b001 The accumulated value is right-shifted by CRS (divided by 2CRS)(1,2)
x MD = ‘b000 or ‘b111 These bits are ignored

Bit 3 – ACLR: A/D Accumulator Clear Command(3)

A/D Accumulator Clear Command(3)

1 Registers ADACC and ADCNT and the AOV bit are cleared
0 Clearing action is complete (or not started)

Bits 2:0 – MD[2:0]: ADC Operating Mode Selection(4)

ADC Operating Mode Selection(4)

111-101 Reserved
100 Low-Pass Filter mode
011 Burst Average mode
010 Average mode
001 Accumulate mode
000 Basic (Legacy) mode