Extended Instruction Syntax

Most of the extended instructions use indexed arguments, using one of the File Select registers and some offset to specify a source or destination register. When an argument for an instruction serves as part of Indexed Addressing, it is enclosed in square brackets (“[ ]”). This is done to indicate that the argument is used as an index or offset. MPASM Assembler will flag an error if it determines that an index or offset value is not bracketed.

When the extended instruction set is enabled, brackets are also used to indicate index arguments in byte-oriented and bit-oriented instructions. This is in addition to other changes in their syntax. For more details, see Extended Instruction Syntax with Standard PIC18 Commands.

Table 1. Extensions to the PIC18 Instruction Set
Mnemonic,

Operands

Description Cycles 16-Bit Instruction Word Status

Affected

Notes
MSb     LSb
ADDULNK k Add literal to FSR2 and return 2 1110 1000 11kk kkkk None 1, 3
MOVSF zs, fd Move zs (12-bit source)

to fd (12-bit destination)

2 1110 1011 0zszszs zszszszs None 2, 3, 4
1111 fdfdfdfd fdfdfdfd fdfdfdfd
MOVSFL zs, fd Move zs (14-bit source)

to fd (14-bit destination)

3 0000 0000 0000 0010 None 2, 3
1111 xxxzs zszszszs zszsfdfd
1111 fdfdfdfd fdfdfdfd fdfdfdfd
MOVSS zs, zd Move zs (source)

to zd (destination)

2 1110 1011 1zszszs zszszszs None 2, 3
1111 xxxx xzdzdzd zdzdzdzd
PUSHL k Store literal at FSR2, decrement FSR2 1 1110 1010 kkkk kkkk None 3

SUBULNK

k Subtract literal from FSR2 and return 2 1110 1001 11kk kkkk None 1, 3
Notes:
  1. 1.If Program Counter (PC) is modified or a conditional test is true, the instruction requires an additional cycle. The extra cycle is executed as a NOP.
  2. 2.Some instructions are multi-word instructions. The extra words of these instructions will be decoded as a NOP, unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.
  3. 3.Only available when extended instruction set is enabled.
  4. 4.fs and fd do not cover the full memory range. 2 MSbs of bank selection are forced to 0b00 to limit the range of these instructions to lower 4k addressing space.