In-Band Interrupt (IBI)

The I3C protocol allows the I3C targets on the bus to generate an interrupt for the Controller to service using the SDA and SCL lines, called In-Band Interrupt (IBI). This makes it possible for the targets on the bus to generate interrupts without using any external interrupt lines.

Each target on the I3C bus has a priority level encoded into its Controller-assigned Dynamic address, with lower value addresses having higher priority levels. This is a natural outcome of the I3C Address Arbitration where address bits with value ‘0’ are prioritized over bits with value ‘1’. This means that when multiple targets request IBI at the same time, targets with lower value addresses (and subsequently higher priority levels) will have their IBI requests processed sooner than targets with higher value addresses.

Important: It is possible that the Target loses arbitration while requesting for IBI when the Controller attempts to write to the Target at the same time. The Controller drives the bus with the Target’s address with R/W = 0 (write, for private write transaction) whereas the Target drives the bus with its own address with R/W = 1 (read, for IBI request). When this happens, the Target loses the arbitration and proceeds forward with the private write transaction with the Controller as described in Private Transaction.
The Target module on this device can perform IBI requests, which is represented in the BCR1 bit (BCR1 = 1). This is communicated to the Controller during the Dynamic Address Assignment procedure or when the Controller requests for it using the GETBCR (Get Bus Characteristics Register) Direct Common Command Code (CCC).
An IBI request can be initiated by setting the IBIREQ bit, after which the Target begins the IBI request process at the next Bus Available condition. Upon successful completion of the IBI request, the IBIREQ bit is cleared, and the IBIDONEIF flag is set.
If the IBI request is unsuccessful, the Target will continue to attempt IBI request at the next Bus Available condition. This process continues until the IBI request is successfully completed, or the number of unsuccessful attempts reaches the Arbitration Request Retry Limit as specified in the I3CxRETRY register and the IBIEIF error flag is set. The IBIREQ bit clears when the IBI request is completed, regardless of the outcome.

The IBI process that the Target follows is described in Figure 1.

Tip: It is recommended to check the value of IBIEN bit in the I3CxEC Events Command register before requesting In-Band Interrupt. The Controller can enable/disable In-Band Interrupt (ENINT/DISINT) globally on the bus by broadcasting the ENEC/DISEC CCC (Enable/Disable Target Events Command) which is reflected in the I3CxEC register.
Important: The Target module will perform an IBI request only when it is operating in I3C SDR mode (OPMD = 0b01) with IBI requests enabled on the bus (IBIEN = 1).
Figure 1. IBI Process Flowchart